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HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V
To ensure secure and trustworthy execution of applications in potentially insecure environments, vendors frequently embed trusted …
Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard
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ConTExT: A Generic Approach for Mitigating Spectre
Out-of-order execution and speculative execution are among the biggest contributors to performance and efficiency of modern processors. …
Michael Schwarz, Moritz Lipp, Claudio Canella, Robert Schilling, Florian Kargl, Daniel Gruss
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Protecting RISC-V Processors against Physical Attacks
RISC-V is an emerging instruction-set architecture suitable for a wide variety of applications, which ranges from simple …
Mario Werner, Robert Schilling, Thomas Unterluggauer, Stefan Mangard
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Securing Conditional Branches in the Presence of Fault Attacks
In typical software, many comparisons and subsequent branch operations are highly critical in terms of security. Examples include …
Robert Schilling, Mario Werner, Stefan Mangard
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Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs
The increasing prevalence of soft errors and security concerns due to recent attacks like rowhammer have caused increased interest in …
Anja F. Karl, Robert Schilling, Roderick Bloem, Stefan Mangard
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Pointing in the Right Direction - Securing Memory Accesses in a Faulty World
Reading and writing memory are, besides computation, the most common operations a processor performs. The correctness of these …
Robert Schilling, Mario Werner, Pascal Nasahl, Stefan Mangard
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High Speed ASIC Implementations of Leakage-Resilient Cryptography
Embedded devices in the Internet-ofThings require encryption functionalities to secure their communication. However, side-channel …
Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini
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Leakage Bounds for Gaussian Side Channels
In recent years, many leakage-resilient schemes have been published. These schemes guarantee security against side-channel attacks …
Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber
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Transparent Memory Encryption and Authentication
Security features of modern (SoC) FPGAs permit to protect the confidentiality of hard- and software IP when the devices are powered off …
Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard
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Multi-Core Data Analytics SoC with a Flexible 1.76 Gbit/s AES-XTS Cryptographic Accelerator in 65 nm CMOS
Embedded systems for Internet-of-Things applications present new challenges to system design. From a hardware design perspective, …
Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti, Stefan Mangard, Luca Benini
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